1. Field of the Invention
The present invention relates to a method for fabricating a flash memory cell. In particular, the invention involves the formation of control gate and floating gate of a flash memory cell.
2. Description of the Prior Art
Complementary metal oxide semiconductor (CMOS) memory is generally categorized into two groups: random access memory (RAM) and read only memory (ROM). RAM is a volatile memory, wherein the stored data disappears when power is off. On the contrary, turning off power does not affect the stored data in a ROM.
In the past few years, market share of ROM has been continuously expanding, and the type attracting the most attention has been flash memory. The fact that a single memory cell is electrically programmable and multiple memory cell blocks are electrically erasable allows flexible and convenient application that are superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory (PROM). Furthermore, fabricating flash memory is cost effective. Having the above advantages, flash memory has been widely applied in consumer electronic products, such as digital cameras, digital video cameras, mobile phones, notebooks, personal stereos and personal digital assistant (PDA).
Since portability of these electrical consumer products is strongly prioritized by consumers, the size of the products must be minimal. As a result, capacity of flash memory must increase, and functions must be maximized while sizes thereof are continuously minimized. Having an increased amount of access data, capacity of memory cells has been enhanced from 4 to 256 MB, and even 1 G byte will become the market trend in the near future. Masks are essential in conventional processes for fabricating flash memory, even for the most critical process of floating gate and control gate.
Conventional process for a split gate flash memory cell is further explained with references to FIGS. 1Axcx9c1G. In FIG. 1A, a p-type silicon substrate 100 is thermal oxidized by local oxidation (LOCOS) to form a field isolation region (not shown). An active area is then formed by separating the field isolation region. Next, a first gate insulating layer 110 is formed on the surface of the substrate 100 within the active area using silicon oxide. Polysilicon is then formed by chemical vapor deposition on the first gate insulating layer 110, followed by doping with suitable dopants to form a first conductive layer 115. Then, a first masking layer 120 is formed using silicon nitride on the first conductive layer 115.
In FIG. 1B, photolithography and etching are performed to remove part of the first masking layer 120, thus defining a first opening 125 and exposing the first conductive layer 115. The remaining first masking layer is represented by 120xe2x80x2. Oxidation is then performed to transform the exposed first conductive layer 115 to an oxide, which is represented by a first insulating layer 130.
Next, in FIG. 1C, isotropic etching is carried out to remove the remaining first masking layer 120xe2x80x2.
The first insulating layer 130 is then used as hard mask to perform anisotropic etching, as shown in FIG. 1D, where part of the first conductive layer 115 and the first insulating layer 110 are removed. The first conductive layer 115 and the first insulating layer 110 underneath the first insulating layer 130 remain and the substrate 100 is exposed. The remaining first conductive layer 115 thus forms a floating gate 140, and the remaining first insulating layer 110 forms a first gate insulating layer 132.
Oxidation or chemical vapor deposition (CVD) is then carried out to form a silicon oxide as the second insulating layer 145, which covers the substrate 100 and surface of the first insulating layer 130 and sidewalls of the floating gate 140 and the first gate insulating layer 132, as shown in FIG. 1E.
Next, chemical vapor deposition is performed to deposit a layer of polysilicon as the conductive layer covering the second insulating layer 145. The conductive layer is then doped with dopant to become conductive, which is represented by the second conductive layer 150, as shown in FIG. 1F.
Photolithography and etching are then accomplished to remove part of the second conductive layer 150 and the second insulating layer 145. The remaining second conductive layer 150 is the control gate 170, and the remaining second insulating layer 145 forms the second gate insulating layer 175. The fabrication of control gate and floating gate are completed at this stage.
Due to the rapid advancement of the integration of memory, the sizes of all elements must be continuously decreased to achieve high integration. Conventional fabrication of flash memory relies upon masks for define sizes and positions of elements, but limitations of mask alignment. causes problems for finer line width, where alignments are difficult. Even tiny misalignment causes shorts for semiconductor elements. Consequently, devices cannot function properly as designed.
Fabrication of memory involves many steps, and production cycles usually last for weeks, even months. Electrical defects are usually not found until later stages. Therefore, when defects caused by misalignment are detected, a great quantity of partially completed products with defects are on the process line, which causes serious losses. Hence, it is the best to be able to handle defects in advance.
In order to overcome the above problems, the invention uses a self-alignment process to form an insulating plug between two floating gates, thus defining the position to form a control gate. This results in easy control of the process and sizes of the control gates and avoids the influence of line width. The length at the bottom of the control gate is consequently assured, which improves the conventional fabrication of flash memory. By having this insulating plug, disagreement among lengths of control gates caused by misalignment when forming control gates is avoided, thus the characteristics of flash memory are improved. The method provided in this invention is useful in fabricating highly-integrated flash memory, wherein defects caused by misalignment in conventional processes are avoided.
The present invention provides a method for fabricating control gate and floating gate of a memory cell, which comprises the following steps: providing a semiconductor substrate; forming a field insulating layer on the surface of the semiconductor substrate to define an active area; forming a first insulating layer on the substrate within the active area; forming a first conductive layer on the first insulating layer; forming a masking layer on the first conductive layer; removing part of the first masking layer to define a first opening and to expose the surface of the first conductive layer; forming a first gate insulating layer on the exposed surface of the first conductive layer by oxidation; removing part of the first masking layer to expose the surface of the first conductive layer; forming a sacrificial layer on the first conductive layer to cover the first gate insulating layer; removing the sacrificial layer between the neighboring first gate insulating layers within the active area to define a second opening and to expose surfaces of the first conductive layer and part of the first gate insulating layer; using the remaining sacrificial layer and the first gate insulating layer as a hard mask to remove the first conductive layer and the first insulating layer within the second opening to form another opening and to expose the surface of the substrate, wherein the opening together with the second opening form a third opening; forming a second insulating layer on surface of the remaining sacrificial layer to fill the third opening; using the remaining sacrificial layer as stop layer to remove the second insulating layer remains on the surface of the sacrificial layer without removing the part within the third opening, which forms an isolating plug; removing the remaining sacrificial layer to expose the remaining first conductive layer and a partial surface of the first gate insulating layer; using the first gate insulating layer and the insulating plug as a hard mask to remove the first conductive layer and the first insulating layer not covered by the first gate isolating layer and the isolating plug, wherein the remaining first conductive layer forms a floating gate and the remaining first insulating layer forms the second gate insulating layer; forming a third insulating layer on surface of the substrate to cover the surface of the first gate insulating layer, the surface and sidewalls of the insulating plug and the sidewalls of the floating gate and the second gate insulating layer; forming a second conductive layer on the surface of the third insulating layer; and using the isolating plug as stop layer to remove part of the second conductive layer and the third insulating layer to expose the the surface of the top part of the insulating plug and the surface of the substrate, wherein the remaining second conductive layer forms a control gate and the remaining third insulating layer forms a tunneling oxide.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.